Typically in a computing system, a clock signal is used to define a time reference for synchronizing operations and movement of data between components. A clock distribution network distributes the clock signal from a common point to various components throughout the computing system. Programmable delay lines and various circuits that modify the clock signal may be employed throughout the clock distribution network to insert clock delays and otherwise modify the clock signal to match timing between different components.
As one example, a clock trimmer circuit 100 that may be employed in a computing system is shown in FIG. 1. The clock trimmer circuit 100 is programmable based on a trim value (TRIM_VALUE) 102 that is applied to a clock input signal (CKIN) 104 to change an amount of delay that is applied to the clock input signal 104. The delay is varied using a cascade of 2-input inverting multiplexers 106. In particular, a first multiplexer in the cascade of multiplexers 106 receives the clock input signal 104 as each of the two inputs. Each of the following multiplexers in the cascade of multiplexers 106 receives the output of the previous multiplexer as one input and the clock input signal 104 as the other input. The trim value 102 is decoded by a decoder 108 to provide a select signal for each of the multiplexers in the cascade of multiplexers 106. The decoded trim value controls which multiplexers select the cascaded clock value that is passed from one multiplexer to the next in the cascade of multiplexers 106, so as to control the amount of delay that is applied to the clock input signal 104. A clock output signal (CKOUT) 110 that is output from the clock trimmer circuit 100 is skewed relative to the clock input signal 104 by the amount of delay that is applied through the cascade of multiplexers 106. Inverting multiplexers are implemented to reduce a delay-step size between multiplexers for finer granularity control. In some cases, the delayed clock signal may be inverted, and the polarity of the delayed clock signal is corrected by a final multiplexer in the cascade of multiplexers 106 before being output.
There are various issues and limitations associated with this approach. For example, the clock trimmer circuit 100 is only configured to add delay to both the rising edge and the falling edge of the clock input signal 104 in lock-step so that the duty cycle is fixed. In other words, the rising edge and the falling edge of the clock input signal are not independently programmable. This feature results in an overall reduction in performance speed of the computing system, since under some conditions the clock frequency is slowed by the lock-step delay.